Hi!
This is just an idea that came to my mind:
I thought about creating vhdl-code for an FPGA (like Xilinx or Altera) that will do the whole crunching or parts of it.
I don't know if the advantage of parallel computing can make up the disadvantage of low clock speed and if there are enough
gates on an FPGA (for example: 5 million gates on a Xilinx Spartan 3 3S5000:
http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3_fpgas/overview.htm)
For writing the vhdl-code I found this:
http://mesl.ucsd.edu/spark/This would be a hardware-SETI-cruncher like a hardware MPEG-Decoder.
What do you think about this?
Is this possible
