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V8 Optimized App

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RottenMutt:
i think i found my problem.  quad cores require G1 stepping NB chips.

Jason G:
Cool, so the question I guess is will the new replacement board have a G1 stepping Northbridge? [ I haven't yet come across that requirement, but am looking :D]

Gecko_R7:

--- Quote from: Gecko_R7 on 19 Oct 2007, 10:24:48 pm ---Noticed your comment regarding latency.

So, on a Q6600 Quad for example, Seti would respond better w/ DDR2-800 @ CL-3 than cranking to higher bandwidth, say DDR2-1200 but having to run CL5?

Is this right?

--- End quote ---


--- Quote from: j_groothu on 19 Oct 2007, 11:11:15 pm ---[PS: As a guesstimate , if 3 cycle latency and 400Mhz (DDR2-800) is 7.5ns , and 5 cycle latency at 600MHz (ddr2-1200) is 8.33ns then a small access will start about 10 % faster with the low latency ddr2 800.

So if I was just doing seti and checking my emails I'd go the ddr2-800 low latency,


--- End quote ---

Thanks Jason.  Makes good sense.  I'm going to give it a whirl and see how it works.
Regards,
Ian

Jason G:

--- Quote from: Gecko_R7 on 20 Oct 2007, 02:36:25 am ---Thanks Jason.  Makes good sense.  I'm going to give it a whirl and see how it works.
Regards,
Ian

--- End quote ---

It'll  be interesting to see  if the theories apply in practice on non-server hardware too.  If low latency's the ticket whatever speed you buy I'll have to improve the ram in my old clunkers  ::)

[Later: came across this while looking for old ddr400 in low latency CAS2... part of advertising for Corsair modules]
--- Quote ---Performance computing enthusiasts have recognized for some time that latency settings may, in fact, have a greater impact on overall system performance than the overall memory bus speed. Indeed, the latency settings have become even more critical due to current system architecture. The latest chip sets have demonstrated that performance is greatest when the memory bus runs at an integral multiple of the front side bus of the processor. So, the optimum memory performance is attained when the memory bus is synchronous with the processor, and latency settings are reduced to the lowest values possible.
--- End quote ---

Gecko_R7:

--- Quote from: j_groothu on 20 Oct 2007, 02:56:26 am ---
--- Quote from: Gecko_R7 on 20 Oct 2007, 02:36:25 am ---Thanks Jason. Makes good sense. I'm going to give it a whirl and see how it works.
Regards,
Ian

--- End quote ---

It'll be interesting to see if the theories apply in practice on non-server hardware too. If low latency's the ticket whatever speed you buy I'll have to improve the ram in my old clunkers ::)


--- End quote ---

I'm actually going to tighten-up a pair of Team Xtreem DDR2-1200 and try to run 1:1 at 400Mhz & CL3-3-3-8 1T w/ FSB 400x8 on P5k Dlx.

Key word is "try".

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